 module epu_read_rxfifo (
    input epu_clk,
    input rst_n,
    input rxfifo_epu_half_full,
    input rxfifo_epu_empty,
    input [11:0] rxfifo_epu_din,
    input [2:0] cdc_counter,
    output reg rxfifo_ready,
    output epu_rxfifo_re
 );
    reg rxfifo_ready_reg;
    
    always@(posedge epu_clk or negedge rst_n)begin
        if(!rst_n) begin
            rxfifo_ready_reg <= 1'b0;
        end 
        else begin
            if (rxfifo_epu_half_full) begin
                rxfifo_ready_reg <= 1'b1;
            end 
            else if(rxfifo_epu_empty && cdc_counter==7) begin
                rxfifo_ready_reg <= 1'b0;
            end
        end
    end

    always@(*) begin
        if(rxfifo_epu_half_full) begin
            rxfifo_ready = 1'b1;
        end
        else if(rxfifo_epu_empty && cdc_counter==7) begin
            rxfifo_ready = 1'b0;
        end
        else begin
            rxfifo_ready = rxfifo_ready_reg;
        end
    end

    assign epu_rxfifo_re = (rxfifo_ready && cdc_counter==0)?1'b1:1'b0;
 endmodule